A modern training accelerator is a package, not a chip. A compute die sits on an interposer alongside several stacks of high-bandwidth memory, each stack made of DRAM layers bonded vertically and connected with through-silicon vias. Every stage of that assembly has its own yield and its own capacity limit.
Why memory is the bottleneck
Large models are memory-bandwidth bound far more often than they are compute bound. Vendors respond by attaching more HBM stacks per package, which raises the memory required per unit sold at exactly the moment demand is rising. The result is that a shortage of stacks translates directly into fewer finished accelerators.
Qualification makes the problem slower to fix. Stacked memory has to be validated with the specific compute die and packaging flow it will ship with, so new capacity does not convert into product for several quarters.
What buyers can watch
Treat announced memory capacity expansions and packaging capacity announcements as the leading indicator for accelerator availability, ahead of any logic foundry commentary. Lead times quoted by system integrators are usually a more honest signal than list prices, which change slowly.