Every cycle the industry treats the next node as routine, and every cycle the first year of production is a fight over capacity. This time the fight is sharper: 2nm-class wafers cost more to make — EUV layer counts, new gate-all-around transistors, denser metal layers — and demand from AI accelerators has added a customer base that did not exist at this scale when 5nm launched.

The allocation math is zero-sum. A wafer committed to a phone SoC is not available for an accelerator die, and the customers with the most capital have been locking in multi-year commitments to hold their positions.

Why it matters

Node allocation is an upstream decision that consumers feel downstream. Which company gets early 2nm capacity determines whose flagship phone or GPU launches first with the process, whose power efficiency claims are real, and whose products slip a quarter waiting for yield maturity.

It also sets pricing. Leading-edge wafer costs have risen with every node, and at 2nm the increase is large enough that chip designers are openly discussing die-size discipline and memory decisions as cost levers, not just performance ones.

How the capacity fight actually works

Foundry allocation is not a spot market. Customers commit through prepayments, long-term agreements and capacity reservations made a year or more before production. Yield learning happens on real products, so the first movers absorb the early-stage defects and get the best cost curves; late movers get mature yield but pay the price in time-to-market.

Meanwhile, not every product belongs on the leading edge. Mid-range phones, most automotive silicon, and the majority of server parts still run on 5nm-class and older nodes, which is exactly why mature-node capacity remains economically rational to expand even as headlines chase 2nm.

Evidence

TSMC's own guidance has described 2nm as its fastest-ramping node to date, with management noting that demand exceeds what the initial fabs can deliver. Supply-chain analysts tracking wafer starts have reported bookings concentrated among the top four to five logic customers, with pricing reported in the range of tens of thousands of dollars per wafer at the leading edge.

Packaging is compounding the constraint: 2nm dies increasingly pair with advanced packaging — CoWoS-class interposers for AI parts — which has its own capacity queue and its own lead times.

The competing read

The bullish reading is that 2nm demand reflects genuine product roadmaps, not inventory panic: gate-all-around transistors deliver real power-performance gains that battery-constrained phones and power-constrained data centers both need.

The bearish reading echoes every prior cycle: prepayments and reservations are made against optimistic forecasts, and any demand disappointment — an AI capex pause, a weak flagship season — leaves customers negotiating down commitments. Both readings agree on one thing: the next two quarters of fab utilization reports will tell us which is right.

What happens next

Watch yield disclosures in TSMC's quarterly calls, the first flagship phone silicon confirmed on 2nm, and whether Intel's and Samsung's competing advanced nodes win design wins that loosen the single-supplier squeeze. The structural fact underneath it all — one company controls the leading edge — remains unchanged, and it is the reason the allocation fight matters more than the node itself.