For half a century, progress in semiconductors was measured by a single number: the size of the features a fab could print on a wafer. That number still matters, but it no longer describes where the industry is stuck. Ask the companies buying AI hardware what limits their supply in 2026 and the answer, more often than not, is packaging — the unglamorous final stage where chips are connected to memory, to each other, and to the outside world.

The shift is structural. Modern AI accelerators are not single chips. They are assemblies: one or more large compute dies, several stacks of high-bandwidth memory, and an interposer or bridge that wires them together, all inside one package. Each of those packages requires a class of factory capacity that barely existed at scale five years ago.

Why it matters

Wafer capacity gets the headlines and the subsidies, but a wafer of AI accelerator dies is worthless until those dies are packaged with HBM. When packaging lines run out of slots, finished wafers queue in storage and delivery times for complete accelerators stretch — which is precisely what buyers reported through 2024 and 2025, when TSMC's CoWoS packaging lines, not its fabs, were the cited constraint on Nvidia's flagship products.

The consequence for policy is significant. Much of the public debate about chip sovereignty in the United States and Europe has focused on leading-edge fabs. Yet a country that fabricates advanced wafers but cannot package them still ships the wafers abroad for assembly — usually to Taiwan — reintroducing the very dependency the fab subsidies were meant to remove. The CHIPS Act program office acknowledged this by funding advanced packaging facilities alongside fabs, including Amkor's Arizona plant.

How it works

Three technologies define the current packaging era. The first is 2.5D integration, typified by TSMC's CoWoS: compute dies and HBM stacks sit side by side on a silicon interposer etched with dense wiring, letting them exchange data at bandwidths a conventional circuit board cannot approach. The second is chiplets — instead of one enormous die, a processor is split into smaller dies that are cheaper to manufacture and then reconnected inside the package, an approach AMD pioneered in its Epyc server line and that the UCIe consortium is now standardizing so chiplets from different vendors can interoperate.

The third is high-bandwidth memory itself. HBM is not soldered to a board like ordinary DRAM; it is a vertical stack of DRAM dies connected by thousands of through-silicon vias, bonded directly next to the compute die. Each successive generation — HBM3, HBM3E, now HBM4 — raises both the bandwidth and the difficulty of assembly, since the stacks must be aligned to micrometer tolerances and the finished package must move enormous heat loads out of a small area.

Yield compounds the problem. If any one die in a twelve-component package fails testing, the whole assembly is lost or downgraded, so packaging houses have invested in 'known good die' testing at every stage — another scarce capability.

Evidence

TSMC's own technology pages describe CoWoS as a 2.5D wafer-level multi-chip packaging platform and list it as the standard vehicle for high-performance computing and AI parts. The UCIe consortium, whose members include Intel, AMD, Arm, TSMC and Samsung, publishes an open specification for die-to-die interconnection explicitly aimed at a multi-vendor chiplet ecosystem. On the memory side, JEDEC published the HBM4 standard (JESD270) defining the interface the next generation of AI accelerators is designed around.

On capacity, the US Department of Commerce's CHIPS program announcements include dedicated funding for advanced packaging — most visibly the award to Amkor for a high-volume packaging facility in Peoria, Arizona — with Commerce framing packaging as a chokepoint in the domestic supply chain. TrendForce and other market trackers have repeatedly reported CoWoS capacity, not wafer starts, as the binding limit on AI accelerator shipments through the recent cycle.

The competing read

Not everyone accepts that packaging is a durable moat rather than a temporary squeeze. Capacity that takes two years to build eventually arrives, and TSMC, Samsung and Intel have all announced aggressive packaging expansions; by the time today's under-construction lines ramp, demand growth could flatten and the shortage could invert into oversupply. There is also an architectural counter-current: if inference workloads shift toward smaller models that fit on single dies with ordinary memory, the most exotic packaging becomes less central.

Both cautions are fair, but the near-term arithmetic still favors the constraint. Every announced flagship AI part from Nvidia, AMD and the major custom-silicon programs assumes HBM and advanced packaging, and design cycles lock those choices in years ahead of production.

What happens next

Watch three things. First, whether UCIe-based multi-vendor chiplets actually ship in volume — a working open ecosystem would loosen the grip of any single packaging house. Second, HBM4 qualification: whichever memory vendors (SK Hynix, Samsung, Micron) pass qualification first will shape accelerator roadmaps into 2027. Third, the pace of packaging construction outside Taiwan, which will determine whether fab subsidies in the US, Japan and Europe translate into genuine end-to-end supply chains or merely relocate the front half of the problem.