The economics that forced the chiplet transition are settled: large monolithic dies waste expensive silicon on defects, and splitting a processor into smaller dies raises yield and lets each piece use the process node that suits it. Every flagship CPU, GPU and AI accelerator now ships as a package of chiplets.
What is not settled is how those chiplets talk to each other — and who gets to sell them.
Why it matters
Today, chiplets are made by the same company that designs the final product: AMD's CPU chiplets talk to AMD's I/O dies over AMD's proprietary fabric. The open-standard vision is different — a market where a startup's accelerator chiplet, a vendor's CPU chiplet and a third party's memory controller could be combined in one package, the way circuit-board components are today. That vision would reshape the industry's structure, lowering the cost of custom silicon and weakening the gatekeepers.
How it works
Die-to-die interconnects must move data between chiplets at board-like bandwidths with a fraction of the power and latency, across the organic or silicon substrate of a package. UCIe — Universal Chiplet Interconnect Express — standardizes the physical and protocol layers for exactly this, with versions covering both standard and advanced packaging. Proprietary alternatives — Nvidia's NVLink-C2C, AMD's Infinity Fabric links, Intel's EMIB-connected fabrics — are tuned to their owners' products and generally beat the standard on power per bit, because their designers control both ends.
The physics is unforgiving: every millimeter of wire costs energy, so the winning interconnect is the one co-designed with the package, the protocol and the software that uses it. That co-design is precisely what an open standard can't assume.
Evidence
The UCIe consortium's member list covers essentially the entire industry, and the specification has advanced through multiple revisions since its 2022 launch, adding packaging options and higher data rates. Test chips and commercial products using UCIe exist. At the same time, the highest-volume chiplet products — AMD's Ryzen and EPYC lines, Apple's M-series Ultra parts, Nvidia's superchips — all run proprietary die-to-die links, and none has announced a switch.
The competing read
Standards advocates note that every successful open interconnect — PCIe, USB, Ethernet — started slower than the proprietary options and won on ecosystem anyway. Pragmatists reply that those standards connected boxes and boards, where the power budget is loose, while die-to-die links live in a regime where a 2x power penalty can kill a product. The emerging consensus is a split: proprietary links inside a vendor's own packages, UCIe at the boundary where chiplets from different companies must meet — defense and aerospace programs, which require multi-vendor sourcing, are the early adopters.
What happens next
Watch the merchant chiplet market: if a credible supplier emerges selling standard UCIe chiplets — memory controllers, I/O dies, accelerators — that others actually integrate, the open model has its foothold. Until then, chiplets remain a manufacturing technique, not a market.