The UALink Consortium, an industry group developing an open scale-up interconnect standard for AI accelerators, announced on April 7, 2026 that it had ratified four specifications at once: definitions for in-network compute, chiplets, manageability and 200G-class performance. The group described the release as underscoring 'industry momentum for open AI scale-up interconnect technology'.
The consortium was formed to give AMD, Intel and other chipmakers a common, non-proprietary way to link accelerators inside a server rack, in direct contrast to Nvidia's NVLink and NVSwitch, which are closed to competitors' chips.
Why it matters
NVLink is one of the biggest reasons Nvidia's GPU clusters outperform rivals at scale: it lets dozens or hundreds of GPUs act as a single accelerator with high-bandwidth, low-latency links, and Nvidia controls the standard end to end. An open alternative that AMD, Intel and cloud providers can build to would reduce lock-in and let mixed-vendor accelerator racks compete on interconnect performance rather than conceding that ground entirely to Nvidia.
How it works
AMD, in a public statement of support published by the consortium, said the 2.0 specification's in-network computing capability, along with the group's first management and chiplet specifications, is meant to lay the groundwork for 'scalable, interoperable' accelerator interconnects. UALink Consortium chairman Kurtis Bowman, who also works at AMD, wrote in March 2026 that training clusters are growing in size and power density while inference pipelines demand predictable throughput, which is the design pressure the new specs target.
Evidence
The Register's coverage of the April announcement noted that UALink is still working through separate physical-layer and protocol specifications to move faster, and pointed out that the consortium was delivering its 2.0 specification before any silicon built to the original 1.0 specification had shipped. That gap between paper specification and shipping hardware is the central open question for the effort's credibility as a near-term NVLink rival.
The competing read
Nvidia's NVLink has years of production deployment behind it and is now on its sixth generation as part of the Vera Rubin platform, while UALink remains pre-silicon for its foundational specification. Critics of open-consortium hardware efforts note that specifications alone do not guarantee interoperable, competitive products ship on a comparable timeline, and that AMD's central role in chairing UALink raises the question of how neutral the standard will be in practice.
What happens next
The consortium's own framing suggests the next milestone to watch is actual UALink-compliant silicon shipping from member companies, since the 2.0 specification builds capabilities on top of a 1.0 base that has not yet reached production. Whether AMD's MI400-series systems or other members' hardware adopt UALink for scale-up networking, rather than proprietary interconnects, will be the practical test of the standard's traction.